The present invention relates to an integrated semiconductor circuit device having a multi-layer wire structure.
With an increase in degree of integration of the semiconductor circuit device, there has been a demand for integrating a logic circuit having complicated functions on one chip. The method of integrating includes the master slice method and the standard cell method.
The former is known as a method of making a gate array. This method is to previously make a large number of elements on a substrate and connect the elements through wires, thus to obtain a desired logic circuit. In this master slice method, the area and shape of the wire region are determined depending upon the degree of integration of the elements.
On the other hand, the standard cell method is to previously arrange in rows a large number of logic-circuit elements called "standard cells" and connect the cells through wires. In this method, the area and shape of the wire region are varied in accordance with the number of wiring tracks. That is, as the scale of a logic circuit is increased, the number of signals are increased. As a result, the number of wiring tracks is increased when the circuit device is laid out, so that the area of the wire region is increased to cause an increase in area of the entire chip. Thus, the degree of integration on the chip is decreased.
In order to solve this problem, the master slice method utilizes a three-layer wire structure, the wire being made of metal, while the standard cell method uses a three-layer wire structure including a polycrystalline-silicon wire, as the wire structure. However, where such a multi-layer wire structure is utilized, the following disadvantages are produced.
Generally, a large-scale integrated semiconductor circuit device is wired by not manually but in accordance with an automatic wiring method that is called "CAD" (computer aided design). For this reason, for facilitating the wiring operation, the wires are distributed only in the wire tracks formed beforehand in the wire region in the form of a matrix. In this case, only a specified wire track is used for each wire layer. Usually, where one of two adjacent wire layers uses a horizontal (lateral) wire track, the other thereof uses a vertical (vertical) wire track. When two wire layers are not adjacent to each other as in case of the first and third wire layers, there is a possibility that the wires of the two wire layers are overlapped one upon the other, since both wire layer use the same wire track. Thus, an additional wire track is required to connect the overlapped wires to each other. As a result, there arises a problem that the area of the wire region is not sufficiently reduced, or that the wire region becomes large in area to cause an increase in the wire resistance, so that the time of delaying the transmission of a signal becomes long.
As an example, reference will now be made to a prior art integrated semiconductor circuit device having a three-layer wire structure in which the first and third wire layers use a vertical track as their respective wire tracks; and the second wire layer uses a horizontal track as its wire track. FIG. 1 is a plan view of a prior art example wherein the first and third layer wires overlap each other, and their wires being connected to the second layer wire.
FIG. 2 is a sectional view taken along the line II--II' of FIG. 1. The first layer (the lowest layer) wire 2 is connected, at a connection position C.sub.1, to the second layer wire 4 in a wire track orthogonal to that in which the first layer wire 2 is located. A third layer wire 8 which is overlapped upon the first layer wire 2 is connected, at a connection position C.sub.2, to a second layer wire 6 in a wire track different from that in which the second layer wire 4 is located. In FIG. 2, the layer which is designated by a reference numeral 1 is a substrate while the layer which is designated by a reference numeral 9 is an insulation layer.
In this way, where the integrated semiconductor circuit device has a three-layer wire structure in which the first layer wire 2 and the third layer wire 8 are partially overlapped one upon the other and intersect the second layer wire at right angles, the connection positions in different wire tracks are required to connect the first and third layers wires to the second layer wire. This hinders the reduction in area of the wire region.